The following note apply for ATtiny13 earlier than revision D only.
Please note that the ATtiny13 E.S. (Engineering Sample) earlier than rev D has an errata concerning special combinations of fuse bits causing the device to lock for further programming. The following combinations of settings/fuse bits will cause this effect:
| Oscillator Setting | Start-up Time Setting | Debugwire and Reset Setting |
|---|---|---|
| 128KHz internal CKSEL[1..0] = 11 | Shortest SUT[1..0]= 00 | Debugwire = Enabled (DWEN = 0) OR Reset = Disabled (RSTDISBL = 0) |
| 9.6 MHz internalCKSEL[1..0] = 10 | Shortest SUT[1..0]= 00 | Debugwire = Enabled (DWEN = 0) OR Reset = Disabled (RSTDISBL = 0) |
| 4.8 MHz internalCKSEL[1..0] = 01 | Shortest SUT[1..0]= 00 | Debugwire = Enabled (DWEN = 0) OR Reset = Disabled (RSTDISBL = 0) |