The connector area contains holes for three pin headers with 1x2, 1x5 and 2x12 pins, to give access to several signals and device pins as shown in tables below. Pin headers with 2.54mm spacing or wires can be soldered in here. A connector for in-circuit programming is surface mounted. Lastly the area contains a board ID system, which is described in more details in the next subsections.
Table 1. Signals that can be found on the 1x2 pin header holes
| Name | Description |
|---|---|
| PACK+(J1) | Battery-pack positive input/output. Also connected to BATT pin |
| PACK-(J2) | Battery-pack negative input/output (ground) |
Table 2. Signals that can be found on the 1x5 pin header holes.
| Name | Description |
|---|---|
| CELL+/ PV4 (J3) | Cells stack positive terminal. / Cell4 positive input |
| PV3 (J4) | Cell3 positive input |
| PV2 (J5) | Cell2 positive input |
| PV1 (J6) | Cell1 positive input |
| CELL- / NV (J7) | Cells stack negative terminal |
Table 3. Signals that can be found on the 2x12 pin header holes.
| Name | Description |
|---|---|
| VREF (J32) | Voltage reference positive pin |
| VREF Gnd (J33) | Voltage reference ground pin |
| VFET (J21) | VFET pin. Supply voltage to the device |
| VREG (J19) | Voltage regulator output pin |
| Reset (J18) | Reset pin |
| Ground (J20) | Ground pin |
| PA3 (J31) | Button switch input pin |
| PA2 (J30) | Not used |
| PA1 (J29) | External NTC 2 ADC input |
| PA0 (J28) | External NTC 1 ADC input |
| PB7 (J17) | SPI MISO pin |
| PB6 (J16) | SPI MOSI pin |
| PB5 (J15) | SPI SCK pin |
| PB4 (J14) | LED 1 output pin |
| PB3 (J13) | LED 2 output pin |
| PB2 (J12) | LED 3 output pin |
| PB1 (J11) | LED 4 output pin |
| PB0 (J10) | LED 5 output pin |
| PC5 (J27) | Not used |
| PC4 (J26) | SMBus/TWI Clock pin |
| PC3 (J25) | SMBus/TWI Data pin |
| PC2 (J24) | 1-wire USART pin (not used) |
| PC1 (J23) | Secondary protection blow input (not used) |
| PC0 (J22) | External protection input pin |
ISP via the SPI interface. Table 2-4 shows connections. Alternative pin names are also noted.
Table 4. ISP connector (J2) signals
| Name | Pin no. | Description |
|---|---|---|
| MISO | 1 | Serial data out (PB7) |
| VCC | 2 | Supply voltage |
| SCK | 3 | Serial clock (PB5) |
| MOSI | 4 | Serial data in (PB6) |
| RESET | 5 | Reset signal (active low) |
| GND | 6 | Ground |