All signals available on the SB20x edge connector are available as test points. These are located next to the SB20x daughter board connector Placement of hardware modules on SB200 (areas within silkscreen rectangles/shape).. 2.54mm pin headers can be mounted to make it easier to hook a scope probe to these test points.
Table 3. Signals on the test points next to the SB20x daughter board connector.
| Test point designator | Signal | Description |
|---|---|---|
| J323 | PV2 | Positive voltage cell 2 |
| J325 | PV1 | Positive voltage cell 1 |
| J326 | (1) | |
| J327 | PV4 | Positive voltage cell 4 |
| J328 | SCL | TWI/SMBus clock |
| J329 | PV3 | Positive voltage cell 3 |
| J330 | SDA | TWI/SMBus data |
| J332 | (1) | |
| J334 | (1) | |
| J336 | (1) | |
| J337 | PA3 | AVR Port A pin 3 |
| J338 | (1) | |
| J339 | PA2 | AVR Port A pin 2 |
| J340 | (1) | |
| J341 | PA1 | AVR Port A pin 1 |
| J342 | (1) | |
| J343 | PA0 | AVR Port A pin 0 |
| J344 | (1) | |
| J345 | Vref | Voltage reference |
| J346 | CELL1BAL_ON | Cell 1 cell balancing enable |
| J347 | GND_ID | GND for ID circuitry |
| J348 | CELL2BAL_ON | Cell 2 cell balancing enable |
| J349 | Vreg | Regulated supply voltage |
| J350 | UART1W | |
| J352 | MISO | SPI master input slave output |
| J354 | MOSI | SPI master output, slave input |
| J356 | SCK | SPI clock |
| J358 | SS | SPI slave select |
| J360 | RESET | Reset to smart battery AVR |
Notes: 1. Test point reserved for future use