Description:

Sets specified bits in register Rd. Performs the logical ORI between the contents of register Rd and constant mask K and places the result in the destination register Rd.

Operation:

(i)Rd ← Rd v K

Syntax: Operands: Program Counter:

(i)SBR Rd,K 16<=d<=31, 0<=K<=255 PC ← PC + 1

16-bit Opcode:

Status Register (SREG) and Boolean Formula:

S: N ⊕ V, For signed tests.

V:0

Cleared

N:R7

Set if MSB of the result is set; cleared otherwise.

Z: $\overline{\mathrm{R7}}•\overline{\mathrm{R6}}•\overline{\mathrm{R5}}•\overline{\mathrm{R4}}$ $•\overline{\mathrm{R3}}•\overline{\mathrm{R2}}•\overline{\mathrm{R1}}•\overline{\mathrm{R0}}$

R (Result) equals Rd after the operation.

Example:

sbr r16,3 ; Set bits 0 and 1 in r16
sbr r17,$F0 ; Set 4 MSB in r17

Words: 1 (2 bytes)

Cycles: 1