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    Description:

    Performs the logical AND between the contents of register Rd and register Rr and places the result in the destination register Rd.

    Operation:

    (i)Rd ← Rd • Rr

    Syntax: Operands: Program Counter:

    (i)AND Rd,Rr 0 ≤ d ≤ 31, 0 ≤ r ≤ 31, PC ← PC + 1

    16-bit Opcode:

    0010

    00rd

    dddd

    rrrr

    Status Register (SREG) and Boolean Formulae:

    I

    T

    H

    S

    V

    N

    Z

    C

    -

    -

    -

    ⇔

    0

    ⇔

    ⇔

    -

    S: N ⊕ V, For signed tests.

    V: 0

    Cleared

    N: R7

    Set if MSB of the result is set; cleared otherwise.

    Z: R7 ¯ • R6 ¯ • R5 ¯ • R4 ¯ • R3 ¯ • R2 ¯ • R1 ¯ • R0 ¯

    Set if the result is $00; cleared otherwise.

    R (Result) equals Rd after the operation.

    Example:

      and r2,r3 ; Bitwise and r2 and r3, result in r2
  ldi r16,1 ; Set bitmask 0000 0001 in r16
  and r2, r16 ; Isolate bit 0 in r2

    Words: 1 (2 bytes)

    Cycles: 1

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